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Dual, Interleaved, Step-Down DC-to-DC Controller with Tracking ADP1823
FEATURES
Fixed-frequency operation: 300 kHz, 600 kHz, or synchronized operation up to 1 MHz Supply input range: 2.9 V to 20 V Interleaved operation results in smaller, low cost input capacitor All-N-channel MOSFET design for low cost 0.85% accuracy at 0C to 70C Soft start, thermal overload, current-limit protection 10 A shutdown supply current Internal linear regulator Lossless RDSON current-limit sensing Reverse current protection during soft start for handling precharged outputs Independent Power OK outputs Voltage tracking for sequencing or DDR termination Available in 5 mm x 5 mm, 32-lead LFCSP
180F 1F PV IN TRK1 TRK2 VREG BST1 DH1 EN1 EN2
TYPICAL APPLICATION CIRCUIT
IN = 12V 180F
BST2 DH2
0.47F IRLR7807Z 1.2V, 6A
0.47F IRLR7807Z 1.8V, 8A
ADP1823
2.2H SW1 2k SW2 CSL2 DL2 PGND2 PGND1 FB1 390pF 2k COMP1 FREQ 4.53k 3900pF GND LDOSD SYNC 3900pF 4.53k FB2 390pF 1k IRFR3709Z 2k 2.2H
560F 2k IRFR3709Z
CSL1 DL1
560F 2k
COMP2
APPLICATIONS
Telecommunications and networking systems Medical imaging systems Base station power Set-top boxes Printers DDR termination
Figure 1. Typical Application Circuit
GENERAL DESCRIPTION
The ADP1823 is a versatile, dual, interleaved, synchronous PWM buck controller that generates two independent output rails from an input of 2.9 V to 20 V. Each controller can be configured to provide output voltages from 0.6 V to 85% of the input voltage and is sized to handle large MOSFETs for pointof-load regulators. The two channels operate 180 out of phase, reducing stress on the input capacitor and allowing smaller, low cost components. The ADP1823 is ideal for a wide range of high power applications, such as DSP and processor core I/O power, and general-purpose power in telecommunications, medical imaging, PC, gaming, and industrial applications. The ADP1823 operates at a pin-selectable, fixed switching frequency of either 300 kHz or 600 kHz, minimizing external component size and cost. For noise-sensitive applications, it can also be synchronized to an external clock to achieve switching frequencies between 300 kHz and 1 MHz. The ADP1823 includes soft start protection to prevent inrush current from the input supply during startup, reverse current protection during soft start for precharged outputs, as well as a unique adjustable lossless current-limit scheme utilizing external MOSFET sensing. For applications requiring power supply sequencing, the ADP1823 also provides tracking inputs that allow the output voltages to track during startup, shutdown, and faults. This feature can also be used to implement DDR memory bus termination. The ADP1823 is specified over the -40C to +85C ambient temperature range, and is available in a 32-lead LFCSP package.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2006 Analog Devices, Inc. All rights reserved.
05936-001
ADP1823 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 Typical Application Circuit ............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 ESD Caution.................................................................................. 5 Functional Block Diagram .............................................................. 6 Pin Configuration and Function Descriptions............................. 7 Typical Performance Characteristics ............................................. 9 Theory of Operation ...................................................................... 13 Input Power ................................................................................. 13 Start-Up Logic............................................................................. 13 Internal Linear Regulator .......................................................... 13 Oscillator and Synchronization ................................................ 13 Error Amplifier ........................................................................... 14 Soft Start ...................................................................................... 14 Power OK Indicator ................................................................... 14 Tracking ....................................................................................... 14 MOSFET Drivers........................................................................ 15 Current Limit.............................................................................. 15 Applications Information .............................................................. 16 Selecting the Input Capacitor ................................................... 16 Selecting the MOSFETS ............................................................ 17 Setting the Current Limit .......................................................... 18 Feedback Voltage Divider ......................................................... 18 Compensating the Voltage Mode Buck Regulator................. 18 Soft Start ...................................................................................... 22 Voltage Tracking......................................................................... 22 Coincident Tracking .................................................................. 22 Ratiometric Tracking ................................................................. 23 Thermal Considerations............................................................ 24 PCB Layout Guidelines.................................................................. 25 LFCSP Package Considerations................................................ 26 Application Circuits ....................................................................... 29 Outline Dimensions ....................................................................... 31 Ordering Guide .......................................................................... 31
REVISION HISTORY
11/06--Rev. 0 to Rev. A Changes to Features and Applications Sections ........................... 1 Changes to Specifications Section.................................................. 3 Changes to Absolute Maximum Ratings Section......................... 5 Replaced Theory of Operation Section ....................................... 13 Added Feedback Voltage Divider Section ................................... 18 Changes to Ratiometric Tracking Section................................... 23 Replaced PCB Layout Guidelines Section................................... 25 Added Application Circuits Section............................................. 29 Changes to Ordering Guide .......................................................... 31 4/06--Revision 0: Initial Version
Rev. A | Page 2 of 32
ADP1823 SPECIFICATIONS
VIN = 12 V, EN = FREQ = PV = VREG = 5 V, SYNC = GND, TJ = -40C to +125C, unless otherwise specified. All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC). Typical values are at TA = 25C. Table 1.
Parameter POWER SUPPLY IN Input Voltage IN Quiescent Current IN Shutdown Current VREG Undervoltage Lockout Threshold VREG Undervoltage Lockout Hysteresis ERROR AMPLIFER FB1, FB2 Regulation Voltage Conditions PV = VREG (using internal regulator) IN = PV = VREG (not using internal regulator) Not switching, IVREG = 0 mA EN1 = EN2 = GND VREG rising Min 5.5 2.9 1.5 10 2.7 0.125 600 Typ Max 20 5.5 3 20 2.9 Unit V V mA A V V mV mV mV mV nA dB MHz A A V V V V mV mV mA mA V F V % % k k mV V 600 +5 100 mV mV nA
2.4
TA = 25C, TRK1, TRK2 > 700 mV TJ = 0C to 85C, TRK1, TRK2 > 700 mV TJ = -40C to +125C, TRK1, TRK2 > 700 mV TJ = 0C to 70C, TRK1, TRK2 > 700 mV
597 591 588 595
FB1, FB2 Input Bias Current Open-Loop Voltage Gain Gain-Bandwidth Product COMP1, COMP2 Sink Current COMP1, COMP2 Source Current COMP1, COMP2 Clamp High Voltage COMP1, COMP2 Clamp Low Voltage LINEAR REGULATOR VREG Output Voltage
603 609 612 605 100
70 20 600 120 2.4 0.75 TA = 25C, IVREG = 20 mA VIN = 7 V to 20 V, IVREG = 0 mA to 100 mA, TA = -40C to +85C IVREG = 0 mA to 100 mA, VIN = 12 V VIN = 7 V to 20 V, IVREG = 20 mA VREG = 4 V VREG < 0.5 V IVREG = 100 mA 4.85 4.75 5.0 5.0 -40 1 220 140 0.7 5.15 5.25
VREG Load Regulation VREG Line Regulation VREG Current Limit VREG Short-Circuit Current IN to VREG Dropout Voltage VREG Minimum Output Capacitance PWM CONTROLLER PWM Ramp Voltage Peak DH1, DH2 Maximum Duty Cycle DH1, DH2 Minimum Duty Cycle SOFT START SS1, SS2 Pull-Up Resistance SS1, SS2 Pull-Down Resistance SS1, SS2 to FB1, FB2 Offset Voltage SS1, SS2 Pull-Up Voltage TRACKING TRK1, TRK2 Common-Mode Input Voltage Range TRK1, TRK2 to FB1, FB2 Offset Voltage TRK1, TRK2 Input Bias Current
100 1
200 1.4
SYNC = GND FREQ = GND (300 kHz) FREQ = GND (300 kHz) SS1, SS2 = GND SS1, SS2 = 0.6 V SS1, SS2 = 0 mV to 500 mV
85
1.3 90 1 90 6 -45 0.8
3
0 TRK1, TRK2 = 0 mV to 500 mV -5
Rev. A | Page 3 of 32
ADP1823
Parameter OSCILLATOR Oscillator Frequency SYNC Synchronization Range SYNC Minimum Input Pulse Width CURRENT SENSE CSL1, CSL2 Threshold Voltage CSL1, CSL2 Output Current Current Sense Blanking Period GATE DRIVERS DH1, DH2 Rise Time DH1, DH2 Fall Time DL1, DL2 Rise Time DL1, DL2 Fall Time DH to DL, DL to DH Dead Time LOGIC THRESHOLDS SYNC, FREQ, LDOSD Input High Voltage SYNC, FREQ, LDOSD Input Low Voltage SYNC, FREQ Input Leakage Current LDOSD Pull-Down Resistance EN1, EN2 Input High Voltage EN1, EN2 Input Low Voltage EN1, EN2 Current Source EN1, EN2 Input Impedance to 5 V Zener THERMAL SHUTDOWN Thermal Shutdown Threshold 2 Thermal Shutdown Hysteresis2 POWER GOOD FB1, UV2 Overvoltage Threshold FB1, UV2 Overvoltage Hysteresis FB1, UV2 Undervoltage Threshold FB1, UV2 Undervoltage Hysteresis POK1, POK2 Propagation Delay POK1, POK2 Off Leakage Current POK1, POK2 Output Low Voltage UV2 Input Bias Current
1 2
Conditions SYNC = FREQ = GND (fSW = fOSC) SYNC = GND, FREQ = VREG (fSW = fOSC) FREQ = GND, SYNC = 600 kHz to 1.2 MHz 1 (fSW = fSYNC/2) FREQ = VREG, SYNC = 1.2 MHz to 2 MHz1 (fSW = fSYNC/2)
Min 240 480 300 600
Typ 300 600
Max 370 720 600 1000 200 +30 56
Unit kHz kHz kHz kHz ns mV A ns ns ns ns ns ns V V A k V V A k C C mV mV mV mV s A mV nA
Relative to PGND CSL1, CSL2 = PGND
-30 44
0 50 100 15 10 15 10 40
CDH = 3 nF, VBST - VSW = 5 V CDH = 3 nF, VBST - VSW = 5 V CDL = 3 nF CDL = 3 nF
2.2 SYNC, FREQ = 0 V to 5.5 V 100 IN = 2.9 V to 20 V IN = 2.9 V to 20 V EN1, EN2 = 0 V to 3.0 V EN1, EN2 = 5.5 V to 20 V 2.0 -0.3 -0.6 100 145 15 VFB1, VUV2 rising VFB1, VUV2 rising 750 50 550 50 8 150 10 1 500 100 0.8 -1.5 0.4 1
VPOK1, VPOK2 = 5.5 V IPOK1, IPOK2 = 10 mA
SYNC input frequency is 2x single channel switching frequency. The SYNC frequency is divided by 2 and the separate phases were used to clock the controllers. Guaranteed by design and not subject to production test.
Rev. A | Page 4 of 32
ADP1823 ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter IN, EN1, EN2 BST1, BST2 BST1, BST2 to SW1, SW2 CSL1, CSL2 SW1, SW2 DH1 DH2 DL1, DL2 to PGND PGND to GND LDOSD, SYNC, FREQ, COMP1, COMP2, SS1, SS2, FB1, FB2, VREG, PV, POK1, POK2, TRK1, TRK2 JA 4-Layer (JEDEC Standard Board) 1, 2 Operating Ambient Temperature 3 Operating Junction Temperature3 Storage Temperature
1 2
Rating -0.3 V to +20 V -0.3 V to +30 V -0.3 V to +6 V -1 V to +30 V -2 V to +30 V SW1 - 0.3 V to BST1 + 0.3 V SW2 - 0.3 V to BST2 + 0.3 V -0.3 V to PV + 0.3 V 2 V -0.3 V to +6 V
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
45C/W -40C < TA< +85C -40C < TJ < +125C -65C to +150C
Measured with exposed pad attached to PCB. Junction-to-ambient thermal resistance (JA) of the package is based on modeling and calculation using a 4-layer board. The junction-to-ambient thermal resistance is application and board-layout dependent. In applications where high maximum power dissipation exists, attention to thermal dissipation issues in board design is required. For more information, please refer to Application Note AN-772, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP). 3 In applications where high power dissipation and poor package thermal resistance are present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA_MAX) is dependent on the maximum operating junction temperature (TJ_MAX_OP = 125oC), the maximum power dissipation of the device in the application (PD_MAX), and the junctionto-ambient thermal resistance of the part/package in the application (JA), is given by the following equation: TA_MAX = TJ_MAX_OP - (JA x PD_MAX).
Rev. A | Page 5 of 32
ADP1823 FUNCTIONAL BLOCK DIAGRAM
IN
ADP1823
VREG 0.6V 0.8V REF 0.75V 0.55V UVLO VREG VREG LDOSD EN1 EN2 FAULT1 CK1 FREQ SYNC RAMP1 CK2 RAMP2 RAMP1 COMP1 + + + - FB1 TRK1 0.6V 0.75V + - + - + 0.8V 0.55V FAULT1 RAMP2 COMP2 + + + - FB2 TRK2 0.6V UV2 SS2 + 0.8V 0.55V FAULT2 - 0.75V + R - + - VREG 50A ILIM2 + - CSL2 POK2 PGND2 - CK2 S Q PV DH2 SW2 BST2 POK1 VREG ILIM1 50A FAULT2 LOGIC THERMAL SHUTDOWN BST1 ILIM2 CK1 S Q DH1 SW1 PV DL1 LINEAR REG
PWM R Q
OSCILLATOR PHASE 1 = 0 PHASE 2 = 180
+ -
PGND1
CSL1
SS1
PWM Q
DL2
GND BOTTOM PADDLE OF LFCSP
05936-002
Figure 2. Functional Block Diagram
Rev. A | Page 6 of 32
ADP1823 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
32 31 30 29 28 27 26 25 COMP1 TRK1 SS1 VREG IN LDOSD EN2 EN1
FB1 SYNC FREQ GND UV2 FB2 COMP2 TRK2
1 2 3 4 5 6 7 8
PIN 1 INDICATOR
TOP VIEW (Not to Scale)
ADP1823
24 23 22 21 20 19 18 17
POK1 BST1 DH1 SW1 CSL1 PGND1 DL1 PV
SS2 POK2 BST2 DH2 SW2 CSL2 PGND2 DL2
9 10 11 12 13 14 15 16
Figure 3. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Mnemonic FB1 SYNC FREQ GND UV2 FB2 COMP2 TRK2 SS2 POK2 BST2 DH2 SW2 CSL2 PGND2 DL2 PV DL1 PGND1 CSL1 SW1 DH1 BST1 POK1 EN1 Description Feedback Voltage Input for Channel 1. Connect a resistor divider from the buck regulator output to GND and tie the tap to FB1 to set the output voltage. Frequency Synchronization Input. Accepts external signal between 600 kHz and 1.2 MHz or between 1.2 MHz and 2 MHz depending on whether FREQ is low or high, respectively. Connect SYNC to ground if not used. Frequency Select Input. Low for 300 kHz or high for 600 kHz. Ground. Connect to a ground plane directly beneath the ADP1823. Tie the bottom of the feedback dividers to this GND. Input to the POK2 Undervoltage and Overvoltage Comparators. For the default thresholds, connect UV2 directly to FB2. For some tracking applications, connect UV2 to an extra tap on the FB2 voltage divider string. Voltage Feedback Input for Channel 2. Connect a resistor divider from the buck regulator output to GND and tie the tap to FB2 to set the output voltage. Error Amplifier Output for Channel 2. Connect an RC network from COMP2 to FB2 to compensate Channel 2. Tracking Input for Channel 2. To track a master voltage, drive TRK2 from a voltage divider from the master voltage. If the tracking function is not used, connect TRK2 to VREG. Soft Start Control Input. Connect a capacitor from SS2 to GND to set the soft start period. Open-Drain Power OK Output for Channel 2. Sinks current when UV2 is out of regulation. Connect a pull-up resistor from POK2 to VREG. Boost Capacitor Input for Channel 2. Powers the high-side gate driver DH2. Connect a 0.22 F to 0.47 F ceramic capacitor from BST2 to SW2 and a Schottky diode from PV to BST2. High-Side (Switch) Gate Driver Output for Channel 2. Switch Node Connection for Channel 2. Current Sense Comparator Inverting Input for Channel 2. Connect a resistor between CSL2 and SW2 to set the current-limit offset. Ground for Channel 2 Gate Driver. Connect to a ground plane directly beneath the ADP1823. Low-Side (Synchronous Rectifier) Gate Driver Output for Channel 2. Positive Input Voltage for Gate Drivers DL1 and DL2. Connect PV to VREG and bypass to ground with a 1 F capacitor. Low-Side (Synchronous Rectifier) Gate Driver Output for Channel 1. Ground for Channel 1 Gate Driver. Connect to a ground plane directly beneath the ADP1823. Current Sense Comparator Inverting Input for Channel 1. Connect a resistor between CSL1 and SW1 to set the current-limit offset. Switch Node Connection for Channel 1. High-Side (Switch) Gate Driver Output for Channel 1. Boost Capacitor Input for Channel 1. Powers the high-side gate driver DH1. Connect a 0.22 F to 0.47 F ceramic capacitor from BST1 to SW1 and a Schottky diode from PV to BST1. Open-Drain Power OK Output for Channel 1. Sinks current when FB1 is out of regulation. Connect a pull-up resistor from POK1 to VREG. Enable Input for Channel 1. Drive EN1 high to turn on the Channel 1 controller, and drive it low to turn off. Enabling starts the internal LDO. Tie to IN for automatic startup.
Rev. A | Page 7 of 32
05936-003
ADP1823
Pin No. 26 27 28 29 30 31 32 Mnemonic EN2 LDOSD IN VREG SS1 TRK1 COMP1 Description Enable Input for Channel 2. Drive EN2 high to turn on the Channel 2 controller, and drive it low to turn off. Enabling starts the internal LDO. Tie to IN for automatic startup. LDO Shut-Down Input. Only used to shut down the LDO in those applications where IN is tied directly to VREG. Otherwise connect LDOSD to GND or leave it open, as it has an internal 100 k pull-down resistor. Input Supply to the Internal Linear Regulator. Drive IN with 5.5 V to 20 V to power the ADP1823 from the LDO. For input voltages between 2.9 V and 5.5 V, tie IN to VREG and PV. Output of the Internal Linear Regulator (LDO). The internal circuitry and gate drivers are powered from VREG. Bypass VREG to ground plane with 1 F ceramic capacitor. Soft Start Control Input. Connect a capacitor from SS1 to GND to set the soft start period. Tracking Input for Channel 1. To track a master voltage, drive TRK1 from a voltage divider to the master voltage. If the tracking function is not used, connect TRK1 to VREG. Error Amplifier Output for Channel 1. Connect an RC network from COMP1 to FB1 to compensate Channel 1.
Rev. A | Page 8 of 32
ADP1823 TYPICAL PERFORMANCE CHARACTERISTICS
95 VIN = 5V VIN = 12V 90
88
EFFICIENCY (%)
92 SWITCHING FREQUENCY = 300kHz 90
85
VIN = 20V VIN = 15V
EFFICIENCY (%)
86 84 82 SWITCHING FREQUENCY = 600kHz
80
75
80
05936-004
0
5
10 LOAD CURRENT (A)
15
20
0
5
10 LOAD CURRENT (A)
15
20
Figure 4. Efficiency vs. Load Current, VOUT = 1.8 V, 300 kHz Switching
95 VOUT = 3.3V 90 VOUT = 1.8V 85 VOUT = 1.2V 80
VREG VOLTAGE (V) EFFICIENCY (%)
Figure 7. Efficiency vs. Load Current, VIN = 12 V, VOUT = 1.8 V
4.980
4.975
4.970
75
4.965
-15
10
35
60
85
LOAD CURRENT (A)
TEMPERATURE (C)
Figure 5. Efficiency vs. Load Current, VIN = 12 V, 300 kHz Switching
94 92 90
EFFICIENCY (%)
Figure 8. VREG Voltage vs. Temperature
4.970
SWITCHING FREQUENCY = 300kHz
4.968 4.966 4.964
88 86 84 82 80 78 SWITCHING FREQUENCY = 600kHz
VREG (V)
4.962 4.960 4.958 4.956 4.954 4.952 5 8 11 14 17 20
05936-009
0
5
10 LOAD CURRENT (A)
15
20
05936-006
4.950
INPUT VOLTAGE (V)
Figure 6. Efficiency vs. Load Current, VIN = 5 V, VOUT = 1.8 V
Figure 9. VREG vs. Input Voltage, 10 mA Load
Rev. A | Page 9 of 32
05936-008
0
5
10
15
20
05936-005
70
4.960 -40
05936-007
70
78
ADP1823
4.960 0.6010
4.956
FEEDBACK VOLTAGE (V)
05936-010
0.6005
0.6000
VREG (V)
4.952
0.5995
4.948
0.5990
4.944
0.5985
0
20
40
60
80
100
-15
10
35
60
85
LOAD CURRENT (mA)
TEMPERATURE (C)
Figure 10. VREG vs. Load Current, VIN = 12 V
Figure 13. Feedback Voltage vs. Temperature, VIN = 12 V
330
5
320
4 VREG OUTPUT (V) FREQUENCY (Hz)
310 300 290 280
3
2
1
270
0
-15
10
35
60
85
LOAD CURRENT (mA)
TEMPERATURE (C)
Figure 11. VREG Current-Limit Foldback
Figure 14. Switching Frequency vs. Temperature, VIN = 12 V
5
T
4
SUPPLY CURRENT (mA)
VREG, AC-COUPLED, 1V/DIV
3
SW1 PIN, VOUT = 1.8V, 10V/DIV
2
SW2 PIN, VOUT = 1.2V, 10V/DIV 200ns/DIV
05936-012
1
2
5
8
11
14
17
20
SUPPLY VOLTAGE (V)
Figure 12. VREG Output During Normal Operation
Figure 15. Supply Current vs. Input Voltage
Rev. A | Page 10 of 32
05936-015
0
05936-014
0
50
100
150
200
250
05936-011
260 -40
05936-013
4.940
0.5980 -40
ADP1823
T
T EXTERNAL CLOCK, FREQUENCY = 1MHz
VOUT1, AC-COUPLED, 100mV/DIV
SW PIN, CHANNEL 1
LOAD ON LOAD OFF 100s/DIV LOAD OFF
05936-016
SW PIN, CHANNEL 2
05936-019
400ns/DIV
Figure 16. 1.5 A to 15 A Load Transient Response, VIN = 12 V
Figure 19. Out-of-Phase Switching, External 1 MHz Clock
T
T
EXTERNAL CLOCK, FREQUENCY = 2MHz
SS1, 500mV/DIV
SW PIN, CHANNEL 1
VOUT1, 1V/DIV
SHORT CIRCUIT APPLIED
05936-017
SW PIN, CHANNEL 2 200ns/DIV
05936-020
SHORT CIRCUIT REMOVED 4ms/DIV
Figure 17. Output Short-Circuit Response
Figure 20. Out-of-Phase Switching, External 2 MHz Clock
T
VIN = 12V
T
VOUT1, 2V/DIV
SWITCH NODE CHANNEL 1
EN1, 5V/DIV
SWITCH NODE CHANNEL 2
05936-018
400ns/DIV
10ms/DIV
Figure 18. Out-of-Phase Switching, Internal Oscillator
Figure 21. Enable Pin Response, VIN = 12 V
Rev. A | Page 11 of 32
05936-021
ADP1823
T VIN, 5V/DIV
EN2 PIN, 5V/DIV
VOUT2, 2V/DIV
VOUT, 2V/DIV
VOUT1, 2V/DIV
05936-022
4ms/DIV
EN1 = 5V
40ms/DIV
Figure 22. Power-On Response, EN Tied to VIN
Figure 24. Coincident Voltage Tracking Response
TRACK PIN VOLTAGE, 200mV/DIV
T
FEEDBACK PIN VOLTAGE, 200mV/DIV
20ms/DIV
Figure 23. Output Voltage Tracking Response
05936-023
Rev. A | Page 12 of 32
05936-024
SOFT START, 1V/DIV
ADP1823 THEORY OF OPERATION
The ADP1823 is a dual, synchronous, PWM buck controller capable of generating output voltages down to 0.6 V and output currents in the tens of amps. The switching of the regulators is interleaved for reduced current ripple. It is ideal for a wide range of applications, such as DSP and processor core I/O supplies, general-purpose power in telecommunications, medical imaging, gaming, PCs, set-top boxes, and industrial controls. The ADP1823 controller operates directly from 2.9 V to 20 V. It includes fully integrated MOSFET gate drivers and a linear regulator for internal and gate drive bias. The ADP1823 operates at a fixed 300 kHz or 600 kHz switching frequency. The ADP1823 can also be synchronized to an external clock to switch at up to 1 MHz per channel. The ADP1823 includes soft start to prevent inrush current during startup, as well as a unique adjustable lossless current limit. The ADP1823 offers flexible tracking for startup and shutdown sequencing. It is specified over the -40C to +85C temperature range and is available in a space-saving, 5 mm x 5 mm, 32-lead LFCSP. While IN is limited to 20 V, the switching stage can run from up to 24 V and the BST pins can go to 30 V to support the gate drive. This can provide an advantage, for example, in the case of high frequency operation from a high input voltage. Dissipation on the ADP1823 can be limited by running IN from a low voltage rail while operating the switches from the high voltage rail.
START-UP LOGIC
The ADP1823 features independent enable inputs for each channel. Drive EN1 or EN2 high to enable their respective controllers. The LDO starts when either channel is enabled. When both controllers are disabled, the LDO is disabled and the IN quiescent current drops to about 10 A. For automatic startup, connect EN1 and/or EN2 to IN. The enable pins are 20 V compliant, but they sink current through an internal 100 k resistor once the EN pin voltage exceeds about 5 V.
INTERNAL LINEAR REGULATOR
The internal linear regulator, VREG, is low dropout, meaning it can regulate its output voltage close to the input voltage. It powers up the internal control and provides bias for the gate drivers. It is guaranteed to have more than 100 mA of output current capability, which is sufficient to handle the gate drive requirements of typical logic threshold MOSFETs driven at up to 1 MHz. Bypass VREG with a 1 F or greater capacitor. Because the LDO supplies the gate drive current, the output of VREG is subjected to sharp transient currents as the drivers switch and the boost capacitors recharge during each switching cycle. The LDO has been optimized to handle these transients without overload faults. Due to the gate drive loading, using the VREG output for other auxiliary system loads is not recommended. The LDO includes a current limit well above the expected maximum gate drive load. This current limit also includes a short-circuit foldback to further limit the VREG current in the event of a fault.
INPUT POWER
The ADP1823 is powered from the IN pin up to 20 V. The internal low dropout linear regulator, VREG, regulates the IN voltage down to 5 V. The control circuits, gate drivers, and external boost capacitors operate from the LDO output. Tie the PV pin to VREG and bypass VREG with a 1 F or greater capacitor. The ADP1823 phase shifts the switching of the two step-down converters by 180, thereby reducing the input ripple current. This reduces the size and cost of the input capacitors. The input voltage should be bypassed with a capacitor close to the highside switch MOSFETs (see the Selecting the Input Capacitor section). In addition, a minimum 0.1 F ceramic capacitor should be placed as close as possible to the IN pin. The VREG output is sensed by the undervoltage lockout (UVLO) circuit to be certain that enough voltage headroom is available to run the controllers and gate drivers. As VREG rises above about 2.7 V, the controllers are enabled. The IN voltage is not directly monitored by UVLO. If the IN voltage is insufficient to allow VREG to be above the UVLO threshold, the controllers are disabled but the LDO continues to operate. The LDO is enabled whenever either EN1 or EN2 is high, even if VREG is below the UVLO threshold. If the desired input voltage is between 2.9 V and 5.5 V, connect the IN directly to the VREG and PV pins, and drive LDOSD high to disable the internal regulator. The ADP1823 requires that the voltage at VREG and PV be limited to no more than 5.5 V. This is the only application where the LDOSD pin is used, and it should otherwise be grounded or left open. LDOSD has an internal 100 k pull-down resistor.
OSCILLATOR AND SYNCHRONIZATION
The ADP1823 internal oscillator can be set to either 300 kHz or 600 kHz. Drive the FREQ pin low for 300 kHz; drive it high for 600 kHz. The oscillator generates a start clock for each switching phase and also generates the internal ramp voltages for the PWM modulation. The SYNC input is used to synchronize the converter switching frequency to an external signal. The SYNC input should be driven with twice the desired switching frequency, as the SYNC input is divided by 2 and the resulting phases were used to clock the two channels alternately.
Rev. A | Page 13 of 32
ADP1823
If FREQ is driven low, the recommended SYNC input frequency is between 600 kHz and 1.2 MHz. If FREQ is driven high, the recommended SYNC frequency is between 1.2 MHz and 2 MHz. The FREQ setting should be carefully observed for these SYNC frequency ranges, as the PWM voltage ramp scales down from about 1.3 V based on the percentage of frequency overdrive. Driving SYNC faster than recommended for the FREQ setting results in a small ramp signal, which could affect the signal-to-noise ratio and the modulator gain and stability. When an external clock is detected at the first SYNC edge, the internal oscillator is reset and clock control shifts to SYNC. The SYNC edges then trigger subsequent clocking of the PWM outputs. The DH rising edges appear about 400 ns after the corresponding SYNC edge, and the frequency is locked to the external signal. Depending on the startup conditions of Channel 1 and Channel 2, either Channel 1 or Channel 2 can be the first channel synchronized to the rising edge of the SYNC clock. If the external SYNC signal disappears during operation, the ADP1823 reverts back to its internal oscillator and experiences a delay of no more than a single cycle of the internal oscillator.
SOFT START
The ADP1823 employs a programmable soft start that reduces input current transients and prevents output overshoot. The SS1 and SS2 pins drive auxiliary positive inputs to their respective error amplifiers, thus the voltage at these pins regulate the voltage at their respective feedback control pins. Program soft start by connecting capacitors from SS1 and SS2 to GND. On startup, the capacitor charges from an internal 90 k resistor to 0.8 V. The regulator output voltage rises with the voltage at its respective soft start pin, allowing the output voltage to rise slowly, reducing inrush current. See the information about Soft Start in the Applications Information section. When a controller is disabled or experiences a current fault, the soft start capacitor is discharged through an internal 6 k resistor, so that at restart or recovery from fault the output voltage soft starts again.
POWER OK INDICATOR
The ADP1823 features open-drain, Power OK outputs, POK1 and POK2, which sink current when their respective output voltages drop, typically 8% below the nominal regulation voltage. The POK pins also go low for overvoltage of typically 25%. Use this output as a logical power-good signal by connecting pull-up resistors from POK1 and POK2 to VREG. The POK1 comparator directly monitors FB1, and the threshold is fixed at 550 mV for undervoltage and 750 mV for overvoltage. However, the POK2 undervoltage and overvoltage comparator input is connected to UV2 rather than FB2. For the default thresholds at FB2, connect UV2 directly to FB2. In a ratiometric tracking configuration, however, Channel 2 can be configured to be a fraction of a master voltage, and thus FB2 regulated to a voltage lower than the 0.6 V internal reference. In this configuration, UV2 can be tied to a different tap on the feedback divider, allowing a POK2 indication at an appropriate output voltage threshold. See the Setting the Channel 2 Undervoltage Threshold for Ratiometric Tracking section.
ERROR AMPLIFIER
The ADP1823 error amplifiers are operational amplifiers. The ADP1823 senses the output voltages through external resistor dividers at the FB1 and FB2 pins. The FB pins are the inverting inputs to the error amplifiers. The error amplifiers compare these feedback voltages to the internal 0.6 V reference, and the outputs of the error amplifiers appear at the COMP1 and COMP2 pins. The COMP pin voltages then directly control the duty cycle of each respective switching converter. A series/parallel RC network is tied between the FB pins and their respective COMP pins to provide the compensation for the buck converter control loops. A detailed design procedure for compensating the system is provided in the Compensating the Voltage Mode Buck Regulator section. The error amplifier outputs are clamped between a lower limit of about 0.7 V and a higher limit of about 2.4 V. When the COMP pins are low, the switching duty cycle goes to 0%, and when the COMP pins are high, the switching duty cycle goes to the maximum. The SS and TRK pins are auxiliary positive inputs to the error amplifiers. Whichever has the lowest voltage, SS, TRK, or the internal 0.6 V reference, controls the FB pin voltage and thus the output. Therefore, if two or more of these inputs are close to each other, a small offset is imposed on the error amplifier. For example, if TRK approaches the 0.6 V reference, the FB sees about 18 mV of negative offset at room temperature. For this reason, the soft start pins have a built-in negative offset and they charge to 0.8 V. If the TRK pins are not used, they should be tied high to VREG.
TRACKING
The ADP1823 features tracking inputs, TRK1 and TRK2, which make the output voltages track another, master voltage. This is especially useful in core and I/O voltage sequencing applications where one output of the ADP1823 can be set to track and not exceed the other, or in other multiple output systems where specific sequencing is required. The internal error amplifiers include three positive inputs, the internal 0.6 V reference voltage and their respective SS and TRK pins. The error amplifiers regulate the FB pins to the lowest of the three inputs. To track a supply voltage, tie the TRK pin to a resistor divider from the voltage to be tracked. See the Voltage Tracking section.
Rev. A | Page 14 of 32
ADP1823
MOSFET DRIVERS
The DH1 and DH2 pins drive the high-side switch MOSFETs. These are boosted 5 V gate drivers that are powered by bootstrap capacitor circuits. This configuration allows the highside, n-channel MOSFET gate to be driven above the input voltage, allowing full enhancement and a low voltage drop across the MOSFET. The bootstrap capacitors are connected from the SW pins to their respective BST pins. The bootstrap Schottky diodes from the PV pins to the BST pins recharge the bootstrap capacitors every time the SW nodes go low. Use a bootstrap capacitor value greater than 100x the high-side MOSFET input capacitance. In practice, the switch node can run up to 24 V of input voltage, and the boost nodes can operate more than 5 V above this to allow full gate drive. The IN pin can be run from 2.9 V to 20 V. This can provide an advantage, for example, in the case of high frequency operation from very high input voltage. Dissipation on the ADP1823 can be limited by running IN from a lower voltage rail while operating the switches from the high voltage rail. The switching cycle is initiated by the internal clock signal. The high-side MOSFET is turned on by the DH driver, and the SW node goes high, pulling up on the inductor. When the internally generated ramp signal crosses the COMP pin voltage, the switch MOSFET is turned off and the low-side synchronous rectifier MOSFET is turned on by the DL driver. Active break-beforemake circuitry, as well as a supplemental fixed dead time, are used to prevent cross-conduction in the switches. The DL1 and DL2 pins provide gate drive for the low-side MOSFET synchronous rectifiers. Internal circuitry monitors the external MOSFETs to ensure break-before-make switching to prevent cross-conduction. An active dead time reduction circuit reduces the break-before-make time of the switching to limit the losses due to current flowing through the synchronous rectifier body diode. The PV pin provides power to the low-side drivers. It is limited to 5.5 V maximum input and should have a local decoupling capacitor. The synchronous rectifiers are turned on for a minimum time of about 200 ns on every switching cycle in order to sense the current. This and the nonoverlap dead times put a limit on the maximum high-side switch duty cycle based on the selected switching frequency. Typically, this is about 90% at 300 kHz switching, and at 1 MHz switching, it reduces to about 70% maximum duty cycle. Because the two channels are 180 out of phase, if one is operating around 50% duty cycle, it is common for it to jitter when the other channel starts switching. The magnitude of the jitter depends somewhat on layout, but it is difficult to avoid in practice. When the ADP1823 is disabled, the drivers shut off the external MOSFETs, so that the SW node becomes three-stated or changes to high impedance.
CURRENT LIMIT
The ADP1823 employs a unique, programmable, cycle-by-cycle lossless current-limit circuit that uses a small, ordinary, inexpensive resistor to set the threshold. Every switching cycle, the synchronous rectifier turns on for a minimum time and the voltage drop across the MOSFET RDSON is measured to determine if the current is too high. This measurement is done by an internal current-limit comparator and an external current-limit set resistor. The resistor is connected between the switch node (that is the drain of the rectifier MOSFET) and the CSL pin. The CSL pin, which is the inverting input of the comparator, forces 50 A through the resistor to create an offset voltage drop across it. When the inductor current is flowing in the MOSFET rectifier, its drain is forced below PGND by the voltage drop across its RDSON. If the RDSON voltage drop exceeds the preset drop on the external resistor, the inverting comparator input is similarly forced below PGND and an overcurrent fault is flagged. The normal transient ringing on the switch node is ignored for 100 ns after the synchronous rectifier turns on, so the overcurrent condition must also persist for 100 ns in order for a fault to be flagged. When an overcurrent event occurs, the overcurrent comparator prevents switching cycles until the rectifier current has decayed below the threshold. The overcurrent comparator is blanked for the first 100 ns of the synchronous rectifier cycle to prevent switch node ringing from falsely tripping the current limit. The ADP1823 senses the current limit during the off cycle. When the current-limit condition occurs, the ADP1823 resets the internal clock until the overcurrent condition disappears. This suppresses the start clock cycles until the overload condition is removed. At the same time, the SS cap is discharged through a 6 k resistor. The SS input is an auxiliary positive input of the error amplifier, so it behaves like another voltage reference. The lowest reference voltage wins. Discharging the SS voltage causes the converter to use a lower voltage reference when switching is allowed again. Therefore, as switching cycles continue around the current limit, the output looks roughly like a constant current source due to the rectifier limit, and the output voltage droops as the load resistance decreases. When the overcurrent condition is removed, operation resumes in soft start mode. See the Setting the Current Limit section for more information.
Rev. A | Page 15 of 32
ADP1823 APPLICATIONS INFORMATION
SELECTING THE INPUT CAPACITOR
The input current to a buck converter is a pulse waveform. It is zero when the high-side switch is off and approximately equal to the load current when it is on. The input capacitor carries the input ripple current, allowing the input power source to supply only the dc current. The input capacitor needs sufficient ripple current rating to handle the input ripple and also ESR that is low enough to mitigate input voltage ripple. For the usual current ranges for these converters, good practice is to use two parallel capacitors placed close to the drains of the high-side switch MOSFETs, one bulk capacitor of sufficiently high current rating as calculated in Equation 1, along with 10 F of ceramic capacitor. Select an input bulk capacitor based on its ripple current rating. If both Channel 1 and Channel 2 maximum output load currents are about the same, the input ripple current is less than half of the higher of the output load currents. In this case, use an input capacitor with a ripple current rating greater than half of the highest load current. Choose the inductor value by the equation
L= VIN - VOUT VOUT I L f SW VIN
(4)
where: L is the inductor value. fSW is the switching frequency. VOUT is the output voltage. VIN is the input voltage. IL is the inductor ripple current, typically 1/3 of the maximum dc load current. Choose the output bulk capacitor to set the desired output voltage ripple. The impedance of the output capacitor at the switching frequency multiplied by the ripple current gives the output voltage ripple. The impedance is made up of the capacitive impedance plus the nonideal parasitic characteristics, the equivalent series resistance (ESR) and the equivalent series inductance (ESL). The output voltage ripple can be approximated with
I RIPPLE >
IL 2
(1)
If the Output 1 and Output 2 load currents are significantly different (if the smaller is less than 50% of the larger), then the procedure in Equation 1 yields a larger input capacitor than required. In this case, the input capacitor can be chosen as in the case of a single phase converter with only the higher load current, so first determine the duty cycle of the output with the larger load current:
D= VOUT VIN
1 VOUT = I L ESR + + 4 f SW ESL 8 f SW C OUT
(5)
(2)
where: VOUT is the output ripple voltage. IL is the inductor ripple current. ESR is the equivalent series resistance of the output capacitor (or the parallel combination of ESR of all output capacitors). ESL is the equivalent series inductance of the output capacitor (or the parallel combination of ESL of all capacitors). Note that the factors of 8 and 4 in Equation 5 would normally be 2 for sinusoidal waveforms, but the ripple current waveform in this application is triangular. Parallel combinations of different types of capacitors, for example, a large aluminum electrolytic in parallel with MLCCs, may give different results. Usually, the impedance is dominated by ESR at the switching frequency, as stated in the maximum ESR rating on the capacitor data sheet, so this equation reduces to
VOUT I L ESR
In this case, the input capacitor ripple current is approximately
I RIPPLE I L D(1 - D)
(3)
where IL is the maximum inductor or load current for the channel and D is the duty cycle. Use this method to determine the input capacitor ripple current rating for duty cycles between 20% and 80%. For duty cycles less than 20% or greater than 80%, use an input capacitor with ripple current rating IRIPPLE > 0.4 IL.
(6)
Selecting the Output LC Filter
The output LC filter attenuates the switching voltage, making the output an almost dc voltage. The output LC filter characteristics determine the residual output ripple voltage. Choose an inductor value such that the inductor ripple current is approximately 1/3 of the maximum dc output load current. Using a larger value inductor results in a physical size larger than is required, and using a smaller value results in increased losses in the inductor and MOSFETs.
Electrolytic capacitors have significant ESL also, on the order of 5 nH to 20 nH, depending on type, size, and geometry, and PCB traces contribute some ESR and ESL as well. However, using the maximum ESR rating from the capacitor data sheet usually provides some margin such that measuring the ESL is not usually required.
Rev. A | Page 16 of 32
ADP1823
In the case of output capacitors where the impedance of the ESR and ESL are small at the switching frequency, for instance, where the output cap is a bank of parallel MLCC capacitors, the capacitive impedance dominates and the ripple equation reduces to Furthermore, the high-side MOSFET transition loss is approximated by the equation
PT VIN I L (t R + t F ) f SW 2
(10)
VOUT
I L 8 COUT f SW
(7)
where tR and tF are the rise and fall times of the selected MOSFET as stated in the MOSFET data sheet. The total power dissipation of the high-side MOSFET is the sum of the previous losses:
PD = PC + PG + PT
Make sure that the ripple current rating of the output capacitors is greater than the maximum inductor ripple current. During a load step transient on the output, the output capacitor supplies the load until the control loop has a chance to ramp the inductor current. This initial output voltage deviation due to a change in load is dependent on the output capacitor characteristics. Again, usually the capacitor ESR dominates this response, and the VOUT in Equation 6 can be used with the load step current value for IL.
(11)
where PD is the total high-side MOSFET power loss. This dissipation heats the high-side MOSFET. The conduction losses may need an adjustment to account for the MOSFET RDSON variation with temperature. Note that MOSFET RDSON increases with increasing temperature. The MOSFET data sheet should list the thermal resistance of the package, JA, along with a normalized curve of the temperature coefficient of the RDSON. For the power dissipation estimated above, calculate the MOSFET junction temperature rise over the ambient temperature of interest:
SELECTING THE MOSFETS
The choice of MOSFET directly affects the dc-to-dc converter performance. The MOSFET must have low on resistance (RDSON) to reduce I2R losses and low gate-charge to reduce switching losses. In addition, the MOSFET must have low thermal resistance to ensure that the power dissipated in the MOSFET does not result in overheating. The power switch, or high-side MOSFET, carries the load current during the PWM on-time, carries the transition loss of the switching behavior, and requires gate charge drive to switch. Typically, the smaller the MOSFET RDSON, the higher the gate charge and vice versa. Therefore, it is important to choose a high-side MOSFET that balances those two losses. The conduction loss of the high-side MOSFET is determined by the equation
TJ = TA + JA PD
(12)
Then calculate the new RDSON from the temperature coefficient curve and the RDSON spec at 25C. A typical value of the temperature coefficient (TC) of the RDSON is 0.004/C, so an alternate method to calculate the MOSFET RDSON at a second temperature, TJ, is
R DSON @ TJ = R DSON @ 25 C [1 + TC(TJ - 25 C )]
(13)
PC I L 2 RDSON
VOUT VIN
Then the conduction losses can be recalculated and the procedure iterated once or twice until the junction temperature calculations are relatively consistent. The synchronous rectifier, or low-side MOSFET, carries the inductor current when the high-side MOSFET is off. For high input voltage and low output voltage, the low-side MOSFET carries the current most of the time, and therefore, to achieve high efficiency it is critical to optimize the low-side MOSFET for small on resistance. In cases where the power loss exceeds the MOSFET rating, or lower resistance is required than is available in a single MOSFET, connect multiple low-side MOSFETs in parallel. The equation for low-side MOSFET power loss is V PLS I L 2 RDSON 1 - OUT VIN (14)
(8)
where: PC = conduction power loss. RDSON = MOSFET on resistance. The gate charge losses are dissipated by the ADP1823 regulator and gate drivers and affect the efficiency of the system. The gate charge loss is approximated by the equation
PG V IN Q G f SW
(9)
where: PG = gate charge power. QG = MOSFET total gate charge. fSW = converter switching frequency. Making the conduction losses balance the gate charge losses usually yields the most efficient choice.
where: PLS is the low-side MOSFET on resistance. RDSON is the parallel combination of the resistances of the lowside MOSFETs. Check the gate charge losses of the synchronous rectifier(s) using the PG equation (Equation 9) to be sure they are reasonable.
Rev. A | Page 17 of 32
ADP1823
SETTING THE CURRENT LIMIT
The current-limit comparator measures the voltage across the low-side MOSFET to determine the load current. The current limit is set through the current-limit resistor, RCL. The current sense pins, CSL1 and CSL2, source 50 A through their respective RCL. This creates an offset voltage of RCL multiplied by the 50 A CSL current. When the drop across the low-side MOSFET RDSON is equal to or greater than this offset voltage, the ADP1823 flags a current-limit event. Because the CSL current and the MOSFET RDSON vary over process and temperature, the minimum current limit should be set to ensure that the system can handle the maximum desired load current. To do this, use the peak current in the inductor, which is the desired current-limit level plus the ripple current, the maximum RDSON of the MOSFET at its highest expected temperature, and the minimum CSL current:
RCL = I LPK R DSON (MAX ) 44 A
COMPENSATING THE VOLTAGE MODE BUCK REGULATOR
Assuming the LC filter design is complete, the feedback control system can then be compensated. Good compensation is critical to proper operation of the regulator. Calculate the quantities in Equation 17 through Equation 58 to derive the compensation values. For convenience, Table 4 provides a summary of the design equations and space for calculations. The information can then be added to a spread-sheet for automated calculation. The goal is to guarantee that the voltage gain of the buck converter crosses unity at a slope that provides adequate phase margin for stable operation. Additionally, at frequencies above the crossover frequency, fCO, guaranteeing sufficient gain margin and attenuation of switching noise are important secondary goals. For initial practical designs, a good choice for the crossover frequency is one tenth of the switching frequency, so first calculate
f CO = f SW 10
(15)
(17)
where ILPK is the peak inductor current. Because the buck converters are usually running fairly high current, PCB layout and component placement may affect the current-limit setting. An iteration of the RCL values may be required for a particular board layout and MOSFET selection. If alternate MOSFETs are substituted at some point in production, the values of the RCL resistor may also need an iteration.
This gives sufficient frequency range to design a compensation that attenuates switching artifacts, while also giving sufficient control loop bandwidth to provide good transient response. The output LC filter is a resonant network that inflicts two poles upon the response at a frequency fLC, so next calculate
f LC = 1 2 LC (18)
FEEDBACK VOLTAGE DIVIDER
The output regulation voltage is set through the feedback voltage divider. The output voltage is reduced through the voltage divider and drives the FB feedback input. The regulation threshold at FB is 0.6 V. The maximum input bias current into FB is 100 nA. For a 0.15% degradation in regulation voltage and with 100 nA bias current, the low-side resistor, RBOT, needs to be less than 9 k, which results in 67 A of divider current. For RBOT, use 1 k to 10 k. A larger value resistor can be used, but results in a reduction in output voltage accuracy due to the input bias current at the FB pin, while lower values cause increased quiescent current consumption. Choose RTOP to set the output voltage by using the following equation:
V - VFB RTOP = R BOT OUT V FB
Generally speaking, the LC corner frequency is about two orders of magnitude below the switching frequency, and therefore about one order of magnitude below crossover. To achieve sufficient phase margin at crossover to guarantee stability, the design must compensate for the two poles at the LC corner frequency with two zeros to boost the system phase prior to crossover. The two zeros require an additional pole or two above the crossover frequency to guarantee adequate gain margin and attenuation of switching noise at high frequencies. Depending on component selection, one zero might already be generated by the equivalent series resistance (ESR) of the output capacitor. Calculate this zero corner frequency, fESR, as
f ESR =
(16)
1 2 R ESR COUT
(19)
where: RTOP is the high-side voltage divider resistance. RBOT is the low-side voltage divider resistance. VOUT is the regulated output voltage. VFB is the feedback regulation threshold, 0.6 V.
This zero is often near or below crossover and is useful in bringing back some of the phase lost at the LC corner.
Rev. A | Page 18 of 32
ADP1823
Figure 25 shows a typical Bode plot of the LC filter by itself.
LC FILTER BODE PLOT
GAIN 0dB
Note that if the converter is being synchronized, the ramp voltage, VRAMP, is lower than 1.3 V by the percentage of frequency increase over the nominal setting of the FREQ pin: 2 f FREQ VRAMP = 1.3 V f SYNC (23)
fLC
fESR
fCO
fSW
FREQUENCY
-40dB/dec
-20dB/dec
AFILTER
The factor of 2 in the numerator takes into account that the SYNC frequency is divided by 2 to generate the switching frequency. For example, if the FREQ pin is set high for the 600 kHz range and a 2 MHz SYNC signal is applied, the ramp voltage is 0.78 V. This increases the gain of the modulator by 4.4 dB in this example. The rest of the system gain needed to reach 0 dB at crossover is provided by the error amplifier and is covered in the compensation design information that follows. The total gain of the system, therefore, is given by AT = AMOD + AFILTER + ACOMP (24) where: AMOD is the gain of the PWM modulator AFILTER is the gain of the LC filter including the effects of the ESR zero ACOMP is the gain of the compensated error amplifier. Additionally, the phase of the system must be brought back up to guarantee stability. Note from the bode plot of the filter that the LC contributes -180 of phase shift. Additionally, because the error amplifier is an integrator at low frequency, it contributes an initial -90. Therefore, before adding compensation or accounting for the ESR zero, the system is already down -270. To avoid loop inversion at crossover, or -180 phase shift, a good initial practical design is to require a phase margin of 60, which is therefore an overall phase loss of -120 from the initial low frequency dc phase. The goal of the compensation is to boost the phase back up from -270 to -120 at crossover. Two common compensation schemes are used, which are sometimes referred to as Type II or Type III compensation, depending on whether the compensation design includes two or three poles. (Dominant pole compensations, or single pole compensation, is referred to as Type I compensation, but unfortunately, it is not very useful for dealing successfully with switching regulators.) If the zero produced by the ESR of the output capacitor provides sufficient phase boost at crossover, Type II compensation is adequate. If the phase boost produced by the ESR of the output capacitor is not sufficient, another zero is added to the compensation network, and thus Type III is used. A general rule to determine the scheme is whether the phase contribution of the ESR zero is greater than 70 at crossover.
PHASE 0
-90 FILTER
05936-025
-180
Figure 25. LC Filter Bode Plot
The gain of the LC filter at crossover can be linearly approximated from Figure 25 as
AFILTER = ALC + A ESR
f AFILTER = -40 dB x log ESR f LC - 20 dBx log f CO f ESR (20)
If fESR fCO, then add another 3 dB to account for the local difference between the exact solution and the linear approximation above. To compensate the control loop, the gain of the system must be brought back up so that it is 0 dB at the desired crossover frequency. Some gain is provided by the PWM modulation itself, so next calculate
V A MOD = 20 log IN V RAMP
V AMOD = 20 log IN 1. 3 V

(21)
For systems using the internal oscillator, this becomes (22)
Rev. A | Page 19 of 32
ADP1823
In Figure 26, the location of the ESR zero corner frequency gives significantly different net phase at the crossover frequency.
PHASE CONTRIBUTION AT CROSSOVER OF VARIOUS ESR ZERO CORNERS GAIN 0dB
For stability, the total phase at crossover is designed to be equal to -120: T = LC + ESR + COMP -120 = -180 + ESR + -90 + P + Z (28) (29)
LC FILTER BODE PLOT
fLC fESR1 fESR2 fESR3 fCO
-40dB/dec
fSW
FREQUENCY
Define phase boost, B, to be the portion of the phase at crossover contributed by the compensator's higher order poles and zeros: B = P + Z (30) (31) B = 150 - ESR
1
-20dB/dec
PHASE 0
Venable showed that an optimum compensation solution was to place the zeros and poles symmetrically around the crossover frequency. He derived a factor known as K with which the frequencies of the compensation zeros and poles may be calculated. K is calculated for the type of compensation selected in Figure 27.
Type II Compensator
G (dB)
1
-1 S
LO
PE
-1 S
LO
PE
-90
PHASE -180
2
fZ
fP
-270
05936-026
-180
3
CHF RZ FROM VOUT RTOP RBOT EA COMP VREF TO PWM
05936-027
CI
Figure 26. LC Filter Bode Plot
Using a linear approximation from Figure 26, the phase contribution of the ESR zero at crossover can be estimated by
ESR = 45 x log 10 x f CO f ESR
VRAMP 0V
(25)
If ESR 70, then Type II compensation is adequate. If ESR < 70, use Type III, as an additional zero is needed. The total phase of the system at crossover is the sum of the contributing elements, namely: T = LC + ESR + COMP where: LC = -180 ESR is as calculated in Equation 25 COMP = -90 + P + Z (26)
Figure 27. Type II Compensation
To calculate K for Type II compensation, use
K = tan B + 45 2
(32)
Values of K between 4 and 15 are practical for implementation; if the selected type of compensation does not yield a reasonable value of K, try the other type. From K, the frequency of the added zeros, fZ, is below crossover by
f CO for Type II K
(27)
fZ =
(33)
Note in the compensator phase expression shown in Equation 27, the -90 term is the phase contributed by the initial integrator pole. The P is the additional phase contributed by the high frequency compensation poles placed above crossover, and Z is the phase contributed by the compensation zeros placed below crossover. For the system to be stable at crossover, phase boost is required from the compensator.
Similarly, the frequency of the added poles, fP, should be above crossover:
f P = f CO K for Type II
(34)
1
D. Venable, "The K Factor: A New Mathematical Tool for Stability Analysis and Synthesis," 1983. Rev. A | Page 20 of 32
ADP1823
Select RTOP between 1 k and 10 k. A good starting value is 2 k. Next, calculate RBOT as
K = tan B + 45 2
and
2
(44)
RBOT
VR = FB TOP VOUT - VFB
0.6 V x RTOP VOUT - 0.6 V
(35)
and
fZ =
f CO K
(45)
R BOT =
(36)
fP = fCO K
(46)
Note that if ratiometric tracking is used, substitute the actual FB voltage for the 0.6 V term used in Equation 36. Calculate the compensator gain needed at crossover to achieve 0 dB total system gain:
AT = A MOD + A FILTER + ACOMP 0 dB = A MOD + A FILTER + ACOMP ACOMP = 0 dB - A MOD - A FILTER
Select RTOP between 1 k and 10 k. A good starting point is 2 k. Next, calculate RBOT as
(37) (38) (39)
RBOT =
R BOT =
VFB RTOP VOUT - VFB
0.6 V x RTOP
(47) (48)
VOUT - 0.6 V
Calculate the value of RZ to achieve that gain:
R ACOMP = 20 x log Z R TOP
R Z = RTOP x 10
ACOMP 20

Note that if ratiometric tracking is used, substitute the actual FB voltage for the 0.6 V term in Equation 48. (40) Calculate the feedforward capacitor to produce the first compensator zero:
C FF =
1 2 RTOP f Z
(41)
(49)
Calculate the integrator cap value to place the compensation zero at the desired frequency:
CI =
1 2 R Z f Z 1 2 R Z f P
Calculate the resistor of the feedforward network to provide the first high frequency compensator pole:
RFF =
1 2 C FF f P
(42)
(50)
Calculate the capacitor value for the high frequency pole:
C HF =
(43)
Calculate the impedance of the feedforward network at the crossover frequency, as this is required to set the gain of the compensator:
Z FF =
1 + RFF 2 C FF f CO
Type III Compensator
G (dB)
-1 S LO PE
(51)
SL +1
E OP
-1 SL O
PE
-90 PHASE -270
fZ
fP
Calculate the compensator gain needed at crossover to achieve 0 dB total system gain: AT = AMOD + AFILTER + ACOMP 0 dB = AMOD + AFILTER + ACOMP ACOMP = 0 dB - AMOD - AFILTER (52) (53) (54)
CHF RFF FROM VOUT RTOP RBOT EA COMP VREF 0V TO PWM
05936-028
CFF
RZ
CI
Calculate the value of RZ to achieve that gain:
RZ ACOMP = 20 x log R || Z FF TOP
R Z = (RTOP || Z FF ) x 10
ACOMP 20

(55)
VRAMP
(56)
Figure 28. Type III Compensation
Calculate the integrator cap value to place the compensation zero at the desired frequency:
CI = 1 2 R Z f Z
(57)
Rev. A | Page 21 of 32
ADP1823
Calculate the capacitor value for the high frequency pole:
C HF = 1 2 R Z f P
(58)
tracking where the output voltage is the same as the master voltage until the master voltage reaches regulation, or ratiometric tracking, where the output voltage is limited to a fraction of the master voltage. In all tracking configurations, the master voltage should be higher than the slave voltage. Note that the soft start time setting of the master voltage should be longer than the soft start of the slave voltage. This forces the rise time of the master voltage to be imposed on the slave voltage. If the soft start setting of the slave voltage is longer, the slave comes up more slowly and the tracking relationship is not seen at the output. The slave channel should still have a soft start capacitor to give a small but reasonable soft start time to protect in case of restart after a current-limit event.
VOUT RTOP COMP RBOT FB
Check that the calculated component values are reasonable. For instance, capacitors smaller than about 10 pF should be avoided. In addition, the ADP1823 error amplifier has finite output current drive, so RZ values less than a few k and CI values greater than 10 nF should be avoided. If necessary, recalculate the compensation network with a different starting value of RTOP. If CHF is too small, start with a smaller value RTOP. If RZ is too small and CI is too big, start with a larger value of RTOP. This compensation technique should yield a good working solution. For a more exact method or to optimize for other system characteristics, a number of references and tools are available from your Analog Devices, Inc., application support team.
SOFT START
The ADP1823 uses an adjustable soft start to limit the output voltage ramp-up period, thus limiting the input inrush current. The soft start is set by selecting the capacitor, CSS, from SS1 and SS2 to GND. The ADP1823 charges CSS to 0.8 V through an internal 90 k resistor. The voltage on the soft start capacitor while it is charging is
VCSS
t = 0.8 V 1 - e RC SS
TRK ERROR AMPLIFIER 0.6V SS DETAIL VIEW OF RTRKT
MASTER VOLTAGE

ADP1823
RTRKB
(59)
Figure 29. Voltage Tracking
The soft start period ends when the voltage on the soft start pin reaches 0.6 V. Substituting 0.6 V for VSS and solving for the number of RC time constants:
t SS 0.6 V = 0.8 V 1 - e 90 k ( CSS)
COINCIDENT TRACKING
The most common application is coincident tracking, used in core vs. I/O voltage sequencing and similar applications. Coincident tracking limits the slave output voltage to be the same as the master voltage until it reaches regulation. Connect the slave TRK input to a resistor divider from the master voltage that is the same as the divider used on the slave FB pin. This forces the slave voltage to be the same as the master voltage. For coincident tracking, use RTRKT = RTOP and RTRKB = RBOT, where RTOP and RBOT are the values chosen in the Compensating the Voltage Mode Buck Regulator section.
MASTER VOLTAGE
VOLTAGE

(60) (61)
t SS = 1.386 RC SS
Because R = 90 k :
C SS = t SS x 8 F/ sec
(62)
where tSS is the desired soft start time in seconds.
VOLTAGE TRACKING
The ADP1823 includes a tracking feature that prevents an output voltage from exceeding a master voltage. This is especially important when the ADP1823 is powering separate power supply voltages on a single integrated circuit, such as the core and I/O voltages of a DSP or microcontroller. In these cases, improper sequencing can cause damage to the load. The ADP1823 tracking input is an additional positive input to the error amplifier. The feedback voltage is regulated to the lower of the 0.6 V reference or the voltage at TRK, so a lower voltage on TRK limits the output voltage. This feature allows implementation of two different types of tracking, coincident
SLAVE VOLTAGE
TIME
Figure 30. Coincident Tracking
As the master voltage rises, the slave voltage rises identically. Eventually, the slave voltage reaches its regulation voltage, where the internal reference takes over the regulation while the TRK input continues to increase and thus removes itself from influencing the output voltage.
Rev. A | Page 22 of 32
05936-030
05936-029
ADP1823
To ensure that the output voltage accuracy is not compromised by the TRK pin being too close in voltage to the 0.6 V reference, make sure that the final value of the master voltage is greater than the slave regulation voltage by at least 10%, or 60 mV as seen at the FB node, and the higher, the better. A difference of 60 mV between TRK and the 0.6 V reference produces about 3 mV of offset in the error amplifier, or 0.5%, at room temperature, while 100 mV between them produces only 0.6 mV or 0.1% offset.
By selecting the resistor values in the divider carefully, Equation 63 shows that the slave voltage output can be made to have a faster ramp rate than that of the master voltage by setting the TRK voltage at the slave larger than 0.6 V and RTRKB greater than RTRKT. Make sure that the master SS period is long enough (that is, sufficiently large SS capacitor) such that the input inrush current does not run into the current limit of the power supply during startup.
RATIOMETRIC TRACKING
Ratiometric tracking limits the output voltage to a fraction of the master voltage. For example, the termination voltage for DDR memories, VTT, is set to half the VDD voltage.
MASTER VOLTAGE
Setting the Channel 2 Undervoltage Threshold for Ratiometric Tracking
If FB2 is regulated to a voltage lower than 0.6 V by configuring TRK2 for ratiometric tracking, the Channel 2 undervoltage threshold can be set appropriately by splitting the top resistor in the voltage divider, as shown in Figure 32. RBOT is the same as calculated for the compensation in Equation 63, and
RTOP = R A + R B
VOLTAGE
SLAVE VOLTAGE
(64)
CHANNEL 2 OUTPUT VOLTAGE UV2 RA
TIME
Figure 31. Ratiometric Tracking
For ratiometric tracking, the simplest configuration is to tie the TRK pin of the slave channel to the FB pin of the master channel. This has the advantage of having the fewest components, but the accuracy suffers as the TRK pin voltage becomes equal to the internal reference voltage and an offset is imposed on the error amplifier of about -18 mV at room temperature. A more accurate solution is to provide a divider from the master voltage that sets the TRK pin voltage to be something lower than 0.6 V at regulation, for example, 0.5 V. The slave channel can be viewed as having a 0.5 V external reference supplied by the master voltage. Once this is complete, then the FB divider for the slave voltage is designed as in the Compensating the Voltage Mode Buck Regulator section, except to substitute the 0.5 V reference for the VFB voltage. The ratio of the slave output voltage to the master voltage is a function of the two dividers:
05936-031
550mV POK2 RB 750mV TO ERROR AMPLIFIER
FB2 RBOT
05936-032
Figure 32. Setting the Channel 2 Undervoltage Threshold
The current in all the resistors is the same:
V V - VFB 2 - VUV 2 VFB 2 = UV 2 = OUT 2 R BOT RB RA
(65)
VOUT V MASTER
1 + = 1 +
RTRKT RTRKB RTOP R BOT
where: VUV2 is 600 mV. VFB2 is the feedback voltage value set during the ratiometric tracking calculations. VOUT2 is the Channel 2 output voltage. Solving for RA and RB:
(63)
R A = RBOT RB = RBOT
(V
OUTA2
- VUV 2 )
Another option is to add another tap to the divider for the master voltage. Split the RBOT resistor of the master voltage into two pieces, with the new tap at 0.5 V when the master voltage is in regulation. This saves one resistor, but be aware that Type III compensation on the master voltage causes the feedforward signal of the master voltage to appear at the TRK input of the slave channel.
(V
VFB 2 VFB 2
(66) (67)
UV 2
- VFB 2 )
Rev. A | Page 23 of 32
ADP1823
THERMAL CONSIDERATIONS
The current required to drive the external MOSFETs comprises the vast majority of the power dissipation of the ADP1823. The on-chip LDO regulates down to 5 V, and this 5 V supplies the drivers. Because the full gate drive current passes through the LDO and then is dissipated in the gate drive, effectively the full gate charge comes from the input voltage and dissipated on the ADP1823 is
PD = V IN f SW (Q DH 1 + Q DL1 + Q DH 2 + Q DL 2 )
The power dissipation heats the ADP1823. As the switching frequency, the input voltage, and the MOSFET size increase, the power dissipation on the ADP1823 increases. Care must be taken not to exceed the maximum junction temperature. To calculate the junction temperature from the ambient temperature and power dissipation: TJ = TA + PD JA (69)
(68)
where: VIN is the voltage applied to IN. fSW is the switching frequency. Q numbers are the total gate charge specifications from the selected MOSFET data sheets.
The thermal resistance, JA, of the package is typically 40C/W depending on board layout, and the maximum specified junction temperature is 125C, which means that at maximum ambient of 85C without airflow, the maximum dissipation allowed is about 1 W. A thermal shutdown protection circuit on the ADP1823 shuts off the LDO and the controllers if the die temperature exceeds approximately 145C, but this is a gross fault protection only and should not be relied upon for system reliability.
Rev. A | Page 24 of 32
ADP1823 PCB LAYOUT GUIDELINES
In any switching converter, some circuit paths carry high dI/dt, which can create spikes and noise. Other circuit paths are sensitive to noise. Still others carry high dc current and can produce significant IR voltage drops. The key to proper PCB layout of a switching converter is to identify these critical paths and arrange the components and copper area accordingly. When designing PCB layouts, be sure to keep high current loops small. In addition, keep compensation and feedback components away from the switch nodes and their associated components. The following is a list of recommended layout practices for the ADP1823, arranged in approximately decreasing order of importance. * The current waveform in the top and bottom FETs is a pulse with very high dI/dt, so the path to, through, and from each individual FET should be as short as possible and the two paths should be commoned as much as possible. In designs that use a pair of D-Pak or SO-8 FETs on one side of the PCB, it is best to counter-rotate the two so that the switch node is on one side of the pair and the high side drain can be bypassed to the low side source with a suitable ceramic bypass capacitor, placed as close as possible to the FETs in order to minimize inductance around this loop through the FETs and capacitor. The recommended bypass ceramic capacitor values range from 1 F to 22 F depending upon the output current. This bypass capacitor is usually connected to a larger value bulk filter capacitor and should be grounded to the PGND plane. GND, PV bypass, VREG bypass, soft start capacitor, and the bottom end of the output feedback divider resistors should be tied to an (almost isolated) small AGND plane. All of these connections should have connections from the pin to the AGND plane that are as short as possible. No high current or high dI/dt signals should be connected to this AGND plane. The AGND area should be connected through one wide trace to the negative terminal of the output filter capacitors. The PGND pin handles high dI/dt gate drive current returning from the source of the low side MOSFET. The voltage at this pin also establishes the 0 V reference for the overcurrent limit protection (OCP) function and the CSL pin. A small PGND plane should connect the PGND pin and the PVCC bypass capacitor through a wide and direct path to the source of the low side MOSFET. The placement of CIN is critical for controlling ground bounce. The negative terminal of CIN needs to be placed very close to the source of the low-side MOSFET. * * Avoid long traces or large copper areas at the FB and CSL pins, which are low signal level inputs that are sensitive to capacitive and inductive noise pickup. It is best to position any series resistors and capacitors as closely as possible to these pins. Avoid running these traces close and parallel to high dI/dt traces. The switch node is the noisiest place in the switcher circuit with large ac and dc voltage and current. This node should be wide to keep resistive voltage drop down. However, to minimize the generation of capacitively coupled noise, the total area should be small. Place the FETs and inductor all close together on a small copper plane in order to minimize series resistance and keep the copper area small. Gate drive traces (DH and DL) handle high dI/dt so tend to produce noise and ringing. They should be as short and direct as possible. If possible, avoid using feedthrough vias in the gate drive traces. If vias are needed, it is best to use two relatively large ones in parallel to reduce the peak current density and the current in each via. If the overall PCB layout is less than optimal, slowing down the gate drive slightly can be very helpful to reduce noise and ringing. It is occasionally helpful to place small value resistors (such as 5 or 10 ) in series with the gate leads, mainly DH traces to the high side FET gates. These can be populated with 0 resistors if resistance is not needed. Note that the added gate resistance increases the switching rise and fall times, and that also increases the switching power loss in the MOSFET. The negative terminal of output filter capacitors should be tied closely to the source of the low side FET. Doing this helps to minimize voltage difference between GND and PGND at the ADP1823. Generally, be sure that all traces are sized according to the current that will be handled as well as their sensitivity in the circuit. Standard PCB layout guidelines mainly address heating effects of current in a copper conductor. While these are completely valid, they do not fully cover other concerns such as stray inductance or dc voltage drop. Any dc voltage differential in connections between ADP1823 GND and the converter power output ground can cause a significant output voltage error, as it affects converter output voltage according to the ratio with the 600 mV feedback reference. For example, a 6 mV offset between ground on the ADP1823 and the converter power output will cause a 1% error in the converter output voltage.
*
*
*
*
*
Rev. A | Page 25 of 32
ADP1823
LFCSP PACKAGE CONSIDERATIONS
The CSP package has an exposed die paddle on the bottom that efficiently conducts heat to the PCB. To achieve the optimum performance from the CSP package, give special consideration to the layout of the PCB. Use the following layout guidelines for the LFCSP package. * The pad pattern is given in Figure 35. The pad dimension should be followed closely for reliable solder joints while maintaining reasonable clearances to prevent solder bridging. The thermal pad of the CSP package provides a low thermal impedance path to the PCB. Therefore, the PCB must be properly designed to effectively conduct the heat away from the package. This is achieved by adding thermal vias to the PCB, which provide a thermal path to the inner or bottom layers. See Figure 35 for the recommended via pattern. Note that the via diameter is small. This prevents the solder from flowing through the via and leaving voids in the thermal pad solder joint. Note that the thermal pad is attached to the die substrate, so the planes that the thermal pad is connected to must be electrically isolated or connected to GND. * The solder mask opening should be about 120 microns (4.7 mils) larger than the pad size, resulting in a minimum 60 microns (2.4 mils) clearance between the pad and the solder mask. The paste mask opening is typically designed to match the pad size used on the peripheral pads of the LFCSP package. This should provide a reliable solder joint as long as the stencil thickness is about 0.125 mm. * * The paste mask for the thermal pad needs to be designed for the maximum coverage to effectively remove the heat from the package. However, due to the presence of thermal vias and the large size of the thermal pad, eliminating voids may not be possible. In addition, if the solder paste coverage is too large, solder joint defects may occur. Therefore, it is recommended to use multiple small openings over a single big opening in designing the paste mask. The recommended paste mask pattern is given in Figure 35. This pattern results in about 80% coverage, which should not degrade the thermal performance of the package significantly. The recommended paste mask stencil thickness is 0.125 mm. A laser cut stainless steel stencil with trapezoidal walls should be used. A no clean, Type 3 solder paste should be used for mounting the LFCSP package. In addition, a nitrogen purge during the reflow process is recommended. The package manufacturer recommends that the reflow temperature should not exceed 220C and the time above liquid is less than 75 seconds. The preheat ramp should be 3C/second or lower. The actual temperature profile depends on the board density; the assembly house must determine what works best.
*
*
*
*
Rev. A | Page 26 of 32
ADP1823
Table 4. Compensation Equations
Equations Calculations (70) (71)
fCO = f LC =
f ESR =
f SW 10 1 2 LC
1 2 R ESR C OUT
(72)
f AFILTER = - 40 dB x log ESR f LC
- 20 dB x log f CO f ESR

(73)
V AMOD = 20 log IN V RAMP 10 x f CO ESR = 45 x log f ESR
(74)
(75) (76)
B = 150 - ESR
If ESR 70 , use Type II compensation. If ESR < 70 , use Type III compensation. Type II Compensation
Calculations
K = tan B + 45 2
(77) (78) (79)
fZ =
fCO
K f P = f CO K
Select RTOP between 1 k and 10 k. A good starting value is 2 k. VFB RTOP R BOT = VOUT - VFB
(80) (81) (82) (83)
ACOMP = 0 dB - AMOD - AFILTER
R Z = RTOP x 10
CI = 1 2 RZ fZ 1 2 R Z fP
ACOMP 20
C HF =
(84)
Rev. A | Page 27 of 32
ADP1823
Type III Compensation Calculations
2
K = tan B + 45 2
(85) (86) (87)
fZ =
f CO K
f P = f CO K
Select RTOP between 1 k and 10 k. A good starting value is 2 k.
R BOT =
C FF =
0.6 V x RTOP VOUT - 0.6 V
1
(88) (89)
2 RTOP f Z
R FF =
Z FF =
1 2 C FF f P
1 2 C FF f CO
(90)
+ R FF
(91) (92) (93)
ACOMP 10 20
ACOMP = 0 dB - AMOD - AFILTER
R Z = (RTOP || Z FF ) x
CI = 1 2 RZ fZ 1 2 R Z fP
(94)
C HF =
(95)
Rev. A | Page 28 of 32
ADP1823 APPLICATION CIRCUITS
The ADP1823 controller can be configured to regulate outputs with loads of more than 20 A if the power components, such as the inductor, MOSFETs and the bulk capacitors, are chosen carefully to meet the power requirement. The maximum load and power dissipation are limited by the powertrain components. Figure 1 shows a typical application circuit that can drive an output load of 8 A. Figure 33 shows an application circuit that can drive 20 A loads. Note that two low-side MOSFETs are needed to deliver the 20 A load. The bulk input and output capacitors used in this example are Sanyo's OSCONTM capacitors, which have low ESR and high current ripple rating. An alternative to the OSCON capacitors
IN = 5.5V TO 20V 1F PV IN TRK1 TRK2 VREG BST1 DH1 SW1 CSL1 DL1 EN1 EN2 D1 BST2 DH2 SW2 CSL2 DL2 0.47F M1 1F CIN1 180F 20V
are the polymer aluminum capacitors that are available from other manufacturers such as United Chemi-con. Aluminum electrolytic capacitors, such as Rubycon's ZLG low-ESR series, can also be paralleled up at the input or output to meet the ripple current requirement. Since the aluminum electrolytic capacitors have higher ESR and much larger variation in capacitance over the operating temperature range, a larger bulk input and output capacitance is needed to reduce the effective ESR and suppress the current ripple. Figure 33 shows that the polymer aluminum or the aluminum electrolytic capacitors can be used at the outputs.
CIN2 180F 20V
1F
D2 0.47F M4
PGND L1 1H 10nF M2 M3 2k 200 1F
1.2V, 20A COUT2 820F 25V x2 1F 5600pF
L2 1H
ADP1823
2k 2k
1.8V, 20A COUT1 1200F 6.3V x3
M6 390 2k
M5
PGND1 PGND2 120nF FB1 COMP1 4.7nF FREQ LDOSD GND SYNC FB2 COMP2 6.8nF 1.5nF
2k 10k
1k 47k
AGND
fOSC = 300kHz
M1, M4: IRLR7807Z L1, L2: TOKO, FDA1254-1ROM COUT1: SANYO, 2R5SEPC820M
D1, D2: VISHAY, BAT54 M2, M3, M5, M6: IRFR3709Z CIN1, CIN2: SANYO, 20SP180M COUT2: RUBYCON, 6.3ZLG1200M10x16
Figure 33. Application Circuit with 20 A Output Loads
Rev. A | Page 29 of 32
05936-033
ADP1823
The ADP1823 can also be configured to drive an output load of less than 1 A. Figure 34 shows a typical application circuit that drives a 1.5 A and a 3 A loads in an all multilayer ceramic capacitor (MLCC) solutions. Notice that the two MOSFETs used in this example are dual-channel MOSFETs in a PowerPAK(R) SO-8 package, which reduces cost and saves layout space. An alternative to using the dual-channel SO-8 package is using two single MOSFETs in SOT-23 or TSOP-6 packages,
IN = 3V TO 4V 1F PV IN TRK1 TRK2 VREG BST1 DH1 SW1 1F 8.2nF M4 1.33k 120nF 2k 6.65k 1.5nF FREQ LDOSD GND SYNC COMP1 COMP2 6.65k 1.5nF IN 4.12k CSL1 DL1 FB1 EN1 EN2 D1 BST2 DH2 SW2 CSL2 DL2 FB2 1.4k M2 2k 120nF 1k 84.5 8.2nF 1F 10F 0.22F M1 1F 10F x2
which are low cost and small in size. For input voltages less than 3.7 V, it is recommended to use MOSFETs that are fully turned on at VGS less than 3 V. Because there is a forward voltage (VF) drop across the Schottky diode D1 or D2, for input voltages less than 3.3 V, the effective voltage to the internal gate drivers may not be enough to drive a large load at the output. A Schottky diode with VF less than 0.5 V at IF of 100 mA is recommended for input voltages less than 3.3 V.
10F x2
1F
D2 0.22F
PGND L1 2.5H
1.0V, 3A COUT3 100F COUT2 47F
L2 2.2H
M3
ADP1823
1.8V, 1.5A COUT1 100F
84.5
PGND1 PGND2
fOSC = 600kHz
AGND L1: SUMIDA, CDRH5D28-2R5NC COUT1, COUT3: MURATA, GRM31CR60J107M D1, D2: CENTRAL SEMI, CMDSH2-4L
05936-034
M1 TO M4: DUAL-CHANNEL SO-8 IRF7331 L2: TOKO, FDV0602-2R2M COUT2: MURATA, GRM31CR60J476M
Figure 34. Application Circuit with all Multilayer Ceramic Capacitors (MLCC)
Rev. A | Page 30 of 32
ADP1823 OUTLINE DIMENSIONS
5.00 BSC SQ 0.60 MAX 0.60 MAX
25 24 32 1
PIN 1 INDICATOR
PIN 1 INDICATOR TOP VIEW 4.75 BSC SQ
0.50 BSC
EXPOSED PAD (BOTTOM VIEW)
17 16 8
3.25 3.10 SQ 2.95
0.50 0.40 0.30 12 MAX
9
0.25 MIN 3.50 REF
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM
1.00 0.85 0.80
SEATING PLANE
0.30 0.23 0.18
0.20 REF
COPLANARITY 0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
Figure 35. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 5 mm x 5 mm Body, Very Thin Quad (CP-32-2) Dimensions shown in millimeters
ORDERING GUIDE
Model ADP1823ACPZ-R7 1 ADP1823-EVAL
1
Temperature Range -40C to +125C
Package Description 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board
Package Option CP-32-2
Z = Pb-free part.
Rev. A | Page 31 of 32
ADP1823 NOTES
(c)2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05936-0-11/06(A)
Rev. A | Page 32 of 32

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